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8-port 10m/100m ethernet switch MTD508 block diagram general description features myson-century technology usa: 4020 moorpark avenue suite 115 san jose, ca, 95117 tel: 408-243-8388 fax: 408-243-3188 sales@myson.com.tw www.myson.com.tw www.century-semi.com rev.1.3 december 2001 page 1 of 19 myson-century technology, inc. taiwan: no. 2, industry east rd. iii, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 the MTD508 complies fully with the ieee802.3, 802.3u and 802.3x specifications and is a non- blocking 8-port 10m/100m ethernet switch device. the MTD508 supports 8 rmii ports for 10m/100m operations. 1mbytes/2mbytes memory interface provides maximum 1365 packet buffers for ethernet packet buffering. up to 8192 address entries are provided by the MTD508, and the MTD508 uses full ethernet address to compare algorithm for minimizing hashing collision events. the MTD508 provides eeprom interface to configure port trunking, port vlan, static entry, 802.3x flow control threshold, flooding port, broadcast control threshold. each MTD508 port supports 10m/100m auto-negotiation by mdc/mdio interface for connecting external phy devices. the MTD508 also provides 10 pins for link/rx activities, packet butter utilization led display functoin. ieee802.3 and ieee802.3u compliant. provides 8 rmii (reduced media independent interface) ports. programmable 1k/8k mac addresses filtering. store and forward switching function and bad packet filtering function. optional back-pressure/802.3x flow control/ flooding control/broadcast control. optional eeprom interface for advanced switch configurations. 1mb/2mb sgram/sdram flexible memory interface. port vlan/trunking. link/rx activities, packet buffer utilization led display. 75mhz for non-blocking for 8-port switch operation. built-in interna/external memory test function. 160-pin pqfp package, 3.3v operating voltage. sdram/ sgram interface memory controller memory port switch logic dma0 dma1 dma2 dma3 dma4 mac0 mac1 mac2 mac3 mac4 rmii5 rmii3 rmii2 rmii1 rmii0 arbiter dma6 dma7 mac5 mac7 rmi7 rmii6 dma5 mac6 rmii4
MTD508 page 2 of 19 myson-century technology system diagram sgram (256k32x1) sgram (512k32x1) sdram (256k32x2) (**programmable) (**optional) eeprom MTD508 leds rmii0-3 rmii4-7 quad physceiver quad transformer rj45 mii management quad physceiver quad transformer rj45
MTD508 page 3 of 19 myson-century technology pin connection 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 crsvd2 txd2_1 txd2_0 txen2 gndo vcco rxd2_0 rxd2_1 crsdv3 txd3_1 txd3_0 txen3 rxd3_0 rxd3_1 crsdv4 col4 txd4_3 txd4_2 txd4_1 txd4_0 txen4 txc4 rxc4 rxdv4 gndi vcci rxd4_0 rxd4_1 rxd4_2 rxd4_3 crsdv5 txd5_1 txd5_0 txen5 rxd5_0 rxd5_1 crsdv6 txd6_1 txd6_0 txen6 ledclk1 dq0 dq1 vcci gndi dq2 dq3 dq4 dq5 dq6 dq7 vcco gndo dq16 dq17 dq18 dq19 vcci gndi dq20 vcco gndo dq21 dq22 dq23 web casb rasb cs0b ba vcci gndi cs1b ad0 ad1 ad2 vcci gndi ad3 ad4 ledclk2 gndo vcco leddata7 leddata6 leddata5 leddata4 leddata3 leddata2 leddata1 leddata0 gndi clk25m vcci sdc sdio eeclk eedata resetb gndo refclk vcco mdio mdc gndi vcci crsdv0 txd0_1 txd0_0 txen0 gndi vcci rxd0_0 rxd0_1 crsdv1 txd1_1 txd1_0 txen1 rxd1_0 rxd1_1 vcco gndo ad5 ad6 ad7 ad8 vcci memclk gndi do8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq24 dq25 dq26 vcco gndo do27 do28 do29 do30 do31 vcci sysclk gndi rxd7_1 rxd7_0 vcci gdni txen7 txd7_0 txd7_1 crsdv7 rxd6_1 rxd6_0 MTD508 160-pin pqfp
MTD508 page 4 of 19 myson-century technology pin description rmii/mii port interface pins name i/o pin description crsdv0 i 147 port0 rmii receive interface signal, crsdv0 is asserted high when port0 media is non-idle. rxd0_0 i 153 port0 rmii receive data bit0. rxd0_1 i 154 port0 rmii receive data bit1. txen0 o 150 port0 rmii transmit enable signal. txd0_0 o 149 port0 rmii transmit data bit0. txd0_1 o 148 port0 rmii transmit data bit1. crsdv1 i 155 port1 rmii receive interface signal, crsdv1 is asserted high when port1 media is non-idle. rxd1_0 i 159 port1 rmii receive data bit0. rxd1_1 i 160 port1 rmii receive data bit1. txen1 o 158 port1 rmii transmit enable signal. txd1_0 o 157 port1 rmii transmit data bit0. txd1_1 o 156 port1 rmii transmit data bit1. crsdv2 i 1 port2 rmii receive interface signal, crsdv2 is asserted high when port2 media is non-idle. rxd2_0 i 7 port2 rmii receive data bit0. rxd2_1 i 8 port2 rmii receive data bit1. txen_2 o 4 port2 rmii transmit enable signal. txd2_0 o 3 port2 rmii transmit data bit0. txd2_1 o 2 port2 rmii transmit data bit1. crsdv3 i 9 port3 rmii receive interface signal, crsdv3 is asserted high when port3 media is non-idle. rxd3_0 i 13 port3 rmii receive data bit0. rxd3_1 i 14 port3 rmii receive data bit1. txen3 o 12 port3 rmii transmit enable signal. txd3_0 o 11 port3 rmii transmit data bit0. txd3_1 o 10 port3 rmii transmit data bit1. crsdv4 i 15 port4 rmii receive interface signal, crsdv2 is asserted high when port4 media is non-idle. rxdv4 i 24 port4 mii receive data valid. in rmii mode, this pin is not used. rxclk4 i 23 port4 mii receive clock signal. in rmii mode, this pin is not used. rxd4_3 i 30 port mii receive data bit3. in rmii mode, this pin is not used. rxd4_2 i 29 port mii receive data bit2. in rmii mode, this pin is not used. rxd4_0 i 27 port mii receive data bit0. rxd4_1 i 28 port mii receive data bit1. txen4 o 21 port4 rmii transmit enable signal.
MTD508 page 5 of 19 myson-century technology txclk4 i 22 port4 rmii transmit clock signal. in rmii mode, this pin is not used. txd4_3 o 17 port4 mii transmit data bit3. in rmii mode, this pin is not used. txd4_2 o 18 port4 mii transmit data bit2. in rmii mode, this pin is not used. txd4_0 o 20 port4 rmii/mii transmit data bit0. txd4_1 o 19 port4 rmii/mii transmit data bit1. col4 i 16 port4 mii collision input. in rmii mode, this pin is not used. clk25m o 155 port4 mii 25mhz clock output. crsdv5 i 31 port5 rmii receive interface signal, crsdv5 is asserted high when port5 media is non-idle. rxd5_0 i 35 port5 rmii receive data bit0. rxd5_1 i 36 port5 rmii received data bit1. txen5 o 34 port5 rmii transmit enable signal. txd5_0 o 33 port5 rmii transmit data bit0. txd5_1 o 32 port5 rmii transmit data bit1. crsdv6 i 37 port6 rmii receive interface signal, crsdv6 is asserted high when port5 media is non-idle. rxd6_0 i 41 port6 rmii receive data bit0. rxd6_1 i 42 port6 rmii received data bit1. txen6 o 40 port6 rmii transmit enable signal. txd6_0 o 39 port6 rmii transmit data bit0. txd6_1 o 38 port6 rmii transmit data bit1. crsdv7 i 43 port7 rmii receive interface signal, crsdv7 is asserted high when port5 media is non-idle. rxd7_0 i 39 port7 rmii receive data bit0. rxd7_1 i 50 port7 rmii received data bit1. txen7 o 46 port7 rmii transmit enable signal. txd7_0 o 45 port7 rmii transmit data bit0. txd7_1 o 44 port7 rmii transmit data bit1. sgram/sdram interface pins name i/o pin description ad[8:0] o 75-78, 81-82, 85-87 memory row/column address bus outputs. ad[7:0] are row/column address[7:0]. ad[8]: this pin should connect to sgram/sdram msb address bit. dq[31:0] i/o 54-58, 61-71, 96-98, 101, 104-107, 110- 115, 118-119 memory data bus. rasb o 93 sgram/sdram row address select. rmii/mii port interface pins name i/o pin description
MTD508 page 6 of 19 myson-century technology casb o 94 sgram/sdram column address select. web o 95 sgram/sdram write enable. ba o 91 sgram/sdram bank select. cs0b o 92 memory chip select 0. cs1b o 88 memory chip select 1. memclk o 73 memory clock output. led interface pins name i/o pin description leddata[7:0] i/o 124-131 led data output. these led pins report ports0?7 link/rx activities using ledclk1 strobe, and report packet buffer utilization status using ledclk2 strobe. leddata [0] [1] [2] [3] [4] [5] [6] [7] ledclk1 lr0 lr1 lr2 lr3 lr4 - - - ledclk2 uti0 uti1 uti2 uti3 uti4 - bfull mfail note: lrn: per port?s link_rxact status; uti0: 5%, uti1: 10%, uti: 20%, uti3: 35%, uti4: 50% and above; bfull: buffer almost full alarm signal; mfail: external memory poer on test failure. ledclk1 i/o 120 led strobe 1. ledclk2 i/o 121 led strobe 2. miscellaneous pins name i/o pin description resetb i 139 system reset input, low active. sysclk i 52 switch core system clock input, using the same clock source with refclk. refclk i 141 rmii reference clock input, using 50mhz. mdc i/o 144 mii management clock inout. mdio i/o 143 mii management data inout. sdc i/o 135 mii register clock inout. sdio i/o 136 mii register data inout. eedata i/o 138 eeprom data input. eeclk i/o 137 eeprom clock output. sgram/sdram interface pins name i/o pin description
MTD508 page 7 of 19 myson-century technology vcc pwr 6, 26, 48, 53, 60, 74, 80, 84, 90, 100, 103, 109, 117, 123, 134, 142, 146, 152 power pins. gnd gnd 5, 25, 47, 51, 59, 72, 79, 83, 89, 99, 102, 108, 116, 122, 132, 140, 145, 151 ground pins. jumper configuration after power on reset name i/o pin description leddata[0] leddata[1] leddata[2] leddata[3] leddata[4] leddata[5] leddata[6] leddata[7] i/o during power on reset duration, these pins are jumper setting pins (pull_high = 1, pull_low = 0). leddata[0]: select sfram/sdram interface, 1:256k32 x 1 or 512k32 is selected; 0: 256k32 x 2 is selected. the default value is ?1?. leddata[1]: configure packet buffer size, 1: 2m bytes buffer size is selected; 0: 1m bytes buffer size is selected. the default value is ?0?. leddata[2]: enable memory test function, 1: enable; 0: disable. the default value is ?1?. leddata[3]: enable aging function, 1: enable; 0: disable. the default value is ?1?. leddata[4]: enable mii polling (mdc/mdio), 1: enable; 0: disable. the default value is ?1?. leddata[5]: enable broadcast storm control, 1: enable; 0: disable. the default value is ?1?. leddata[6]: enable backpressure function, 1: enable; 0: disable. the default value is ?1?. leddata[7]: enable 802.3x flow control function (in full mode), 1: enable; 0: disable. the default value is ?1?. ledclk1 i/o during power on reset duratoion, this in is a jumper setting pin (pull_high = 1, pull_low = 0). ledclk1: select 1k or 8k address entry table, 1: 8k entry address is selected; 0: 1k address entry is selected. the default value is ?1?. ledclk2 i/o during power on reset duration, this in is a jumper setting pin (pull_high = 1, pull_low = 0). ledclk2: enable eeprom interface, 1: enable; 0: disable. the default value is ?1?. eedata i/o during power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). eedata: enable eeprom auto-load configuration function while eeprom interface is enabled, 1: enable; 0: disable. the default value is ?1?. miscellaneous pins name i/o pin description
MTD508 page 8 of 19 myson-century technology txen[2:0] i/o during power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). txen[2:0]: uplink port (flooding port) 0-7 selection. the default value is ?000?. txen[3] i/o during power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). txen[3]: enable flooding control, 1: enable; 0: disable. the default value is ?1?. txen[4] i/o during power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). txen[4]: enable vlan tag 1522 bytes receiving, 1: enable; 0: disable. the default value is ?0?. txen[5] i/o during power on reset duration, this pin is a jumper setting in (pull_high = 1, pull_low = 0). txen[5]: select port7 full/half ability while port7 is in fx mode, 1: port7 full duplex is selected; 0: port7 half duplext is selected. the default value is ?0?. txen[7] i/o during power on reset duration, this pin is a jumper setting in (pull_high = 1, pull_low = 0). txen[7]: enable port7 fx mode, 1: enable; 0: disable. the default value is ?0?. sdc i/o during power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). sdc: port4 mii/rmii interface selection, 1: port4 mii interface is selected, and in the meantime, port5, 6, 7 are automatically disabled; 0: port4 rmii interface is selected. the default value is ?0?. eeclk i/o during power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). eeclk: scan mode enable for debugging purpose, 1: scan mode enable, 0: scan mode disable. the default value is ?0?. mdc i/o during power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). mdc: fast mode enable, 1: fast mode enable; 0: fast mode disable. the default value is ?0?. jumper configuration after power on reset name i/o pin description
MTD508 page 9 of 19 myson-century technology functional description the MTD508 is an 8-port 10/100mbps fast ethernet switch controller. it is a low-cost solution for eight ports fast ethernet soho switch design. no cpu interface is required. after power on reset, the MTD508 provides an auto load configuration setting function through a 2-wire serial eeprom interface to access external eeprom device, and the MTD508 can easily be configured to support port-trunking, port-vlan, static entry, 802.3x flow control threshold setting, flooding port assignment... etc. functions. the following descriptions are the MTD508?s major function blocks overview. packet store and fowarding the MTD508 uses simple store and forward algorithm as packet switching method. input packet from ports will be stored to external memory first, while packet is good for forwarding (crc check okay, 64bytes < length < 1518bytes, not local packets, in the same vlan group), if this packet?s da hits, then forward this packet to the destination port, otherwise this packet will be broadcasted. learing and routing the MTD508 supports 1k or 8k mac entries for switching. dynamic address learing is performed by each good unicast packet is completely received. the static address learning achieved by eeprom configuration. on the other hand, the routing process is performed whenever the packet?s da is captured. if the da cannot get a hit result, the packet is going to switch broadcast or forward to the dedicated port according to the flooding control selection. aging only the dynamic address entries are scheduled int he aging machine. if one station does not transmit any packet for a period of time, the belonging mac address will be kicked out from the address table. the aging out time can be programmed through the eeprom auto load configuration. (default value is 300 seconds.) buffer queue management the buffer queue manager is implemented to manage the external shared memory (use sdram/sgram) for packet buffering. the main function of the buffer queue manager is to maintain the linked list sonsisted of buffer ids, which are used to show the corresponding memory address for each incoming packet. in addition, the buffer queue manager monitors the rested free spaces status of the external memory. if the packet storage achieves the predefined threshold value, the buffer queue manager will raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission id queue overflow happening. the MTD508 provides 802.3x flow control in full duplex mode and back pressure control in half duplex mode. full duplex 802.3x flow control in full duplex mode, the MTD508 supports the standard flow control defined in ieee802.3x standard. it enables the stopping of remote node transmissions via a pause frame information interaction. when the ?802.3x flow control enable? bit is set during power on reset (leddata[7] pin is external pull_high), it enables the MTD508 supporting 802.3x flow control function in full duplex mode; when output port buffer queue?s on-using value reaches the initialization setting threshold value (recommended xon_th = 74h when using 2mbytes external memory; xon_th = 2eh when using 1mbytes external memory), the MTD508 will send out a pause packet with pause time equal to fff to stop the remote node transmission. when the output port buffer queue?s on-using value reduces to the initialization threshold value (recommended xoff_th = 30h when using 2mbytes external memory; xoff_th = 18h when using 1mbytes external memory), the MTD508 will also send a pause packet with pause time equal to zero to inform the remote node to retransmit packet. half duplex back pressure control in halp duplex mode, the MTD508 provides a back pressure control mechanism to avoid dropping packets during network congestion. when the ?back pressure control enable? bit is set during power on reset (leddata[6]pin is
MTD508 page 10 of 19 myson-century technology external pull_high), it enables the MTD508 supporting back pressure function in half-duplex mode. when output port buffer queue?s on-using value reaches the initialization setting threshold value (same with the xon_th value), the MTD508 will send a jam pattern in the input port when it senses an incoming packet, thus forcing a collision to inform the remote node transmission back off and will effectively avoid dropping packets. if the ?back pressure control enable? bit is not set, and there is no free buffer queue available for the incoming packets, the incoming packets will be dropped. mii polling the MTD508 supports phy management through the serial mdio/mdc interface. after power on reset, the MTD508 writes related abilities to the advertisement register 4 of connected phy devices and restarts the auto- negotiation procedure via mdio/mdc interface using the predefined phy addresses increasingly from ?01000?b to ?01100?b. the MTD508 will lperiodically and continuously poll and update the link status and link partner?s ability including speed, duplex mode, and 802.3x flow control capable status of the connected phy devices through mdio/mdc serial interface. mac and dma engine the MTD508?s mac performs all functions in ieee802.3 protocol, such as frame formatting, frame stripping, crc checking, bad packet dropping, deferring to line traffic, and collision handling. the mac rx_engine checks incoming packets and drops the bad packet including crc error, alignment error, short packet (less than 64 bytes) and long packet (more than 1518 bytes when the ?vlan tag 1522 bytes receive enable? bit is set during power on reset). before transmission, the mac tx_engine will constantly monitor the line traffic using deferring procedure. only if it has been idle for a half duplex mode, mac engine will detect collision; if a collision is detected, the mac tx-engine will transmit a jam pattern and then dalay the re-transmission for a random time period determined by the back-off algorithm (the MTD508 implements the truncated exponential back-off algorithm defined in ieee802.3 standard). for the full duplex mode, collision signal is ignored. the MTD508?s dma engine performs the packets non-blocking transmportation between mac engine and external memory according to a high speed swetching procedure. the switching procedure is completed by address learning/routing process and buffer queue management operation. eeprom interface the MTD508 provides and auto load configuration setting function through a 2-wire serial eeprom interface to access external eeprom device (24c02) after power on reset. the MTD508 can easily be configured to support port-trunking, port-vlan, static entry, 802.3x flow control threshold setting, flooding port assignment... etc functions. the following table is the eeprom contents mapping: name eeprom address eeprom content description recommended value under basic operation eob 00 last eeprom content address value 8h13 agelow 01 aging time bit [7:0] 8h2c agehigh 02 aging time bit [15:8] 8h01 vlan0 03 port0 vlan register 8hfe vlan1 04 port1 vlan register 8hfd vlan2 05 port2 vlan register 8hfb vlan3 06 port3 vlan register 8hf7 vlan4 07 port4 vlan register 8hef reserved 08 reserved 8hdf reserved 09 reserved 8hbf
MTD508 page 11 of 19 myson-century technology port based vlan the MTD508 supports vlan configuration by port based methodology. one port selects the certain ports to form its vlan group by configuring the vlan register. the packet (including broadcast packet) is not forwarded to the destination port whose vlan group is different from the source port. port trunking the port trunking function can also be implemented by vlan registers. one trunk port isolates the packeting transmitting and receiving from the other trunk ports, which perform a logical trunk topology. the non-trunk port should choose only one trunk port for transmitting, which can achieve the load balancing and maintain the packet sequences. memory interface two kinds of external memory interfaces can be selected by user, namely 1mbyte memory (256k32 x 1) and 2mbyte (256k32 x 2 or 512k x 1). maximum 2mbyte external memory can be used for packet buffering. ?-10? speed grade of sgram/sdram device is recommended. the following table is the sgram application pin connection: reserved 0a reserved 8h7f uplink10 0b bit[7:4] the flooding port_no of port1; bit[3:0] the flooding port_no of port0. *ex1: bit[7:4] = ?oo11?b, it means that if the incoming packet of port1 gets the ?un-routed? result, then this incoming packet will be flooded to port3. *ex2: bit[3:0] = ?0111?b, it means that if the incoming packet of port0 gets the ?un-routed? result, then this incoming packet will be flooded to port7. (note: setting value to ?4hf? means flooding to all the other ports; setting value to ?4h8? to ?4he? is forbidden.) 8h0f uplink32 0c bit[7:4] the flooding port_no of port3; bit[3:0] the flooding port_no of port2. (note: setting value to ?4hf? means flooding to all ports; setting value to ?4h8? to ?4he? is forbidden.) 8h00 uplink54 0d bit[7:4] reserved; bit[3:0] the flooding port_no of port4. (note: setting value to ?f? means flooding to all the other ports; setting value to ?8? to ?h? is forbidden.) 8h00 reserved 0e reserved 8h00 broadcast th 0f broadcast threshold 8hff xon th 10 xon threshold 8h74 xoff th 11 xoff threshold 8h30 disport 12 disable port 8h00 system control 13 system control byte: bit[0] enhanced back pressure enable; bit[7:1] reserved. 8h00 reserved 14 - 1f none staticsa1 20 -26 address 26 bit[2:0] port id; address 25 bit [7:0] ~ address 20 bit[7:0] static sa[47:0]. staticsa2 27 -2d address 2d bit[2:0] port id; address 2c bit [7:0] ~ address 20 bit[7:0] static sa[47:0]. name eeprom address eeprom content description recommended value under basic operation
MTD508 page 12 of 19 myson-century technology internal mii registers access and control the MTD508 supports 2 serial pins (sdio/sdc) for internal registers access and control. the detailed registers information is presented in the section on ?internal mii registers?. led display the MTD508 uses 10 pins to output two kinds of led display: leddata[7:0], ledclk1, and ledclk2. ledclk1 rising edge and leddata[7:0] are used to report port7-0 link/receive activity led status. ledclk2 rising edge and leddata[4:0] are used to report packet buffer utilization rating, and leddata[7] is used to report external memory test result (after power reset, the MTD508 will test external sdram automatically), and leddata[6] reports the buffer almost full alarm signal. memory type memory chip no. a[8] cs0b cs1b 256k32 x 1 a8 cs0b nc 236k32 x 2 a8 cs0b cs1b 512k32 x 1 a9 cs0b a8
MTD508 page 13 of 19 myson-century technology internal mii registers the MTD508 implements 10 mii global registers and 4-per-dot registers, defined as the following tables: table 1. mii registers global registers reg no. bit name r/w description default 0 ctlreg0 r/w control register 0 8-0 bit[0]: 1 switch to port 0 registers; bit[1]: 1 switch to port 1 registers; bit[2]: 1 switch to port 2 registers; bit[3]: 1 switch to port 3 registers; bit[4]: 1 switch to port 4 registers; bit[5]: reserved; bit[6]: reserved; bit[7]: reserved; bit[8]: 1 switch to global registers. 9h100 12-9 scan mode select 3-0. 15-13 scan port select. 1 ctlreg1 r/w control register 1 16h3084 7-0 xon xon threshold. 15-8 xoff xoff threshold. while eeprom is enabled, this register?s content will be updated by eeprom read xon/xoff threshold data automatically. after eeprom read is done, this register can be read/write by management cmd. the default value is ?16h3084? (2m memory) or ?16h1838? (1m memory). 2 ctlreg2 r/w control register 2 16?d300 15-0 aging bit[15:0] can specify aging time. while eeprom is enabled, this register?s content will be updated by eeprom read aging timer data automatically. after eeprom read is done, this register can be read/write by management cmd. 3 ctlreg3 r/w control register 3 16h000f 15-0 uplink reg0 bit[15:12] specify uplink port id of port 3; bit[11:8] specify uplink port id of port 2; bit[7:4] specify uplink port id of port 1; bit[3:0] specify uplink port id of port 0. the default value is ?16h000f?. note: the write sequence of this register is jumper setting eeprom content mii management command. 4 ctlreg4 r/w control register 4 16h0 15-0 uplink reg1 bit[15:12]: reserved; bit[11:8]: reserved; bit[7:4]: reserved; bit[3:0]: specify port id of port 4. the default value is ?16h0?. note: the write sequence of this register is jumper setting eeprom content mii management command. 5 ctlreg5 r/w control register 5 16hff 7-0 bit[7:0]: specify broadcast threshold. 8 bit[8]: enable enhance backpressure. 15-9 reserved. note: this register can be written by eeprom content or mii management command. 6 stsreg0 ro/rc status register 0
MTD508 page 14 of 19 myson-century technology ?r/w? means read/writable. 7-0 bit[4:0]: output port4-0 rxdma fifofull; bit[5]: reserved. 15-8 bit[12:8]: output port4-0 txdma tpur (fifoempty); bit[15:13]: reserved. 7 stsreg1 ro status register 1 0: bufbistdone; 1: bufbisterr; 2: bufinitdone; 3: addrtblbistdone; 4: addrtblbisterr; 5: lthtblbistdone; 6: lthtblbisterr; 7: membistdone; 8: membisterr; 9: eedone; 10: freecntls0; 15-11: reserved. 8 ctlreg7 r/w control register 7 7-0 bit[4:0]: output mii polling port4-0 flow control information; bit[7:5]: reserved. 15-8 bit[12:8]: output mii polling port 4-0 link information; bit[15:13]: reserved. ?1? means flow control enable or link good. 9 ctlreg8 r/w control register 8 7-0 bit[4:0]: output mii polling port4-0 speed information; bit[7:5]: reserved. 15-8 bit[12:8]: output mii polling port4-0 full information; bit[15:13]: reserved. ?1? means 100m or full duplex. port registers reg no. bit name r/w description default 1 stsreg1 ro status register 1 10-0 bit[10:0]: output port tx queue head value. 15-11 reserved. 2 stsreg2 ro status register 2 10-0 bit[10:0]: output port tx queue tail value. 15-11 reserved. 3 stsreg3 ro status register 3 10-0 bit[10:0]: output port tx queue count value. 15-11 reserved. 4ctlreg1r/w 7-0 bit[7:0]: select port vlan group. 15-8 reserved. global registers reg no. bit name r/w description default
MTD508 page 15 of 19 myson-century technology absolute maximum ratings recommended operating conditions dc electrical characteristics (under recommended operating conditions and vcc = 3.0 ~ 3.6v, tj = 0 to 115 c) symbol parameter rating unit v cc power supply voltage -0.3 to 3.6 v v in input voltage -0.3 to v cc + 0.3 v v out output voltage -0.3 to v cc + 0.3 v t stg storage temperature -55 to 150 c symbol parameter min typ max unit v cc power supply 3.0 3.3 3.6 v v in input voltage 0 - v cc v t a free-air ambient temperature 0 25 70 c symbol parameter conditions min typ max unit i il input leakage current no pull-up or down -1 1 ua i oz tri-state leakage current -1 1 ua c in input capacitance 2.8 pf c out output capacitance 2.7 4.9 pf c bid3 bi-directional buffer capacitance 2.7 4.9 pf v il input low voltage cmos 0.3*v cc v v ih input high voltage cmos 0.7*v cc v v oh output high voltage i ol = 2, 4, 6, 8, 12, 16, 24ma 0.4 v v ol output low voltage i oh = 2, 4, 6, 8, 12, 16, 24ma 2.4 v r i input pull-up/down resistance v il = 0v or v ih = v cc 75 kohm
MTD508 page 16 of 19 myson-century technology electrical characteristics figure-1 rmii timing figure-2 mii timing symbol parameter min typ max unit t1 rmii input setup time 1 ns t2 rmii input hold time 1 ns t3 rmii output setup time 3 ns t4 rmii output hold time 5 ns symbol parameter min typ max unit t5 mii input setup time 10 ns t6 mii input hold time 10 ns t7 mii output setup time 3 ns t8 mii output hold time 5 ns refclk crsdv rxd[1:0] txen txd[1:0] t1 t2 t3 t4 valid valid refclk0 crs0/rxdv0 rxd0[3:0] t5 t6 valid t7 t8 valid txclk0 txen0 txd0[3:0]
MTD508 page 17 of 19 myson-century technology figure-3 memory write timing figure-4 memory read timing symbol parameter min typ max unit t5 memory clock cycle 12 ns t6 memory command/address/data setup time 6 ns t7 memory command/address/data hold time 2 ns t8 row active to burst write 2 clk memclk rasb casb web ad[8:0] dq[31:0] valid valid t5 t6 t7 t8 t6 t7 t6 t7 t6 t7 memclk rasb casb web ad[8:0] dq[31:0] t6 t7 t5 t6 t7 t6 t7 t9 t10 valid valid valid t8
MTD508 page 18 of 19 myson-century technology figure-5 eeprom timing figure-6 led interface symbol parameter min typ max unit t10 memory read data setup time 2 ns t11 memory read data hold time 2 ns symbol parameter min typ max unit t11 eeprom clock cycle 10 us t12 eeddata input setup time 1 ns t13 eedata input hold time 1 ns symbol parameter min typ max unit t14 eeprom clock cycle 20 us t15 eeddata input setup time 5 us t16 eedata input hold time 5 us eeclk eedata t12 t11 t13 valid ledclk1 ledclk2 leddata valid valid valid t14 t15 t16
MTD508 page 19 of 19 myson-century technology package outline symbol dimensions in millimeters dimensions in inches min nom max min nom max a - - 3.683 - - 0.145 a1 0.152 - - 0.006 - - a2 2.73 2.85 2.97 0.107 0.112 0.117 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 - 0.20 0.004 - 0.008 d 23.00 23.20 23.40 0.906 0.913 0.921 d1 19.90 20.00 20.10 0.783 0.787 0.791 e 17.00 17.00 17.40 0.669 0.677 0.685 e1 13.90 13.90 14.10 0.547 0.551 0.555 e 0.50bcs 0.020bcs l 0.73 0.88 1.03 0.029 0.035 0.041 l1 1.60bcs 0.063bcs y - - 0.10 - - 0.004 z0 -7 0 -7 h d d 160 121 120 81 80 41 40 1 a1 a2 e a1 a2 a c l l1 b e h e

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